Visible to Intel only — GUID: ilq1682710714021
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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
Visible to Intel only — GUID: ilq1682710714021
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3.4.3. Reset Signals
Signal Name | Clocks Domains | Direction | Description |
---|---|---|---|
i_tx_reset | asynchronous | input | TX reset input for TX PMA and TX datapath. Must be kept asserted until o_tx_reset_ack is asserted. |
i_rx_reset | asynchronous | input | RX reset input for RX PMA and RX datapath. Must be kept asserted until o_rx_reset_ack is asserted. |
o_tx_reset_ack | asynchronous | output | TX fully in reset indicator. o_tx_reset_ack indicates that the PMA is in reset. It asserts after the assertion of i_tx_reset, and deasserts after the deassertion of i_tx_reset. |
o_rx_reset_ack | asynchronous | output | RX fully in reset indicator. o_rx_reset_ack indicates that the PMA is in reset. It asserts after the assertion of i_rx_reset and deasserts after the deassertion of i_rx_reset. |
o_tx_ready | asynchronous | output | Status port to indicate when TX PMA and TX datapath are reset successfully and ready for data transfer. |
o_rx_ready | asynchronous | output | Status port to indicate when RX PMA and RX datapath are reset successfully and ready for data transfer. |
o_tx_am_gen_start 27 | asynchronous | output | When using FEC, indicates when to start sending alignment markers. This clears after i_tx_am_gen_2x_ack is asserted. |
i_tx_am_gen_2x_ack 27 | asynchronous | input | When using FEC, you must indicate to the reset sequencer at least 2 alignment markers were sent since o_tx_am_gen_start is asserted. This signal should be deasserted after o_tx_am_gen_start is deasserted. |
o_src_rs_req[N-1:0] | asynchronous | output | Request signal from Soft Reset Controller (SRC) to GTS Reset Sequencer Intel FPGA IP for reset operation. Asserts when there is a request to toggle reset. |
i_src_rs_grant [N-1:0] | asynchronous | input | Grant signal from GTS Reset Sequencer Intel FPGA IP to SRC. Asserts when the reset request is granted by Reset Sequencer Intel FPGA IP. |
i_pma_cu_clk[M-1:0] | clock | input | PMA Control Unit clock source, one per GTS bank for each side of the device. This clock port must be connected from the GTS Reset Sequencer Intel FPGA IP. |
27 This signal is only valid for RS-FEC.