Visible to Intel only — GUID: ndc1708719279669
Ixiasoft
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
Visible to Intel only — GUID: ndc1708719279669
Ixiasoft
8.3.5. Running BER Tests
After you create the transceiver links for debugging, you can run BER tests by selecting the pin for the TX and RX channels you want to test in your Collection tab. Then, follow the steps below to start running the BER test:
- Open Toolkit Parameters tab as shown in the following figure, and make sure to enable the Auto refresh UI. You cannot see the status signals being updated such as RX CDR locked to data signal if you do not enable Auto refresh UI. You can also set the period at which the UI (User Interface) updates in seconds in the Auto refresh period (seconds) parameter.
Figure 91. Toolkit Parameters Tab
- In the Channel Parameters tab, select the PRBS pattern in the TX and RX channels.
- Set the TX Equalization Parameters. Key in the values, click Set Parameters. To load the values, click Get Parameters.
- Choose which Loopback mode you want to test. Select Off from the dropdown menu if you are using external loopback.
- Click Start in the TX Channel to start the Hard PRBS generator.
- To stop the test, click Stop in the RX Channel and TX Channel.
- To reset the channel, click TX Reset PMA and RX Reset PMA.
- You can monitor the BER by checking the status of BER in the RX Channel tab.
The following figure shows the setup and results for an example BER test for the GTS PMA.
Figure 92. Example BER Test Setup and Results
You can set parameters, start PRBS generator, stop PRBS checker or reset across multiple channels simultaneously from the Status Table. Choose the desired channels, right-click, select Edit Parameters or the Action sub-menu.
Note: After changing TX or RX equalization parameters across multiple channels from the Edit Parameters window, you need to right click on the selected channels, select Actions ➤ Receiver or Transmitter ➤ Analog ➤ Set Parameters in order to load in the updated value.