GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1. IP Requirements

The GTS Reset Sequencer Intel FPGA IP must be instantiated for each side of the device that uses transceivers. Refer to the Transceiver Architecture chapter for more information. Based on your design you must instantiate one or two of instances of the IP:
  • One GTS Reset Sequencer Intel IP instance if your design uses transceivers on one side of the device.
  • Two GTS Reset Sequencer Intel IP instances if your design uses transceivers on both sides of the device.
The following table shows the logic usage in the FPGA fabric of the GTS Reset Sequencer Intel FPGA IP.
Table 61.  Logic Usage of the GTS Reset Sequencer Intel FPGA IP (For Agilex™ 5 E-Series and D-Series Devices)
Device Family ALM34 ALUT Logic Register M20K
Agilex™ 5 E-Series (12 Lanes) 88 107 113 0
Agilex™ 5 D-Series (16 Lanes) 108 122 137 0
34 Logic utilization is lower for fewer channel applications.