GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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3.3.1. Preset IP Parameter Settings

The IP parameter editor provides preset settings for the GTS PMA/FEC Direct PHY Intel FPGA IP. You can specify the preset settings as a starting point for your design. To apply the preset parameters, double-click the preset name, and click Apply as shown in the following figure.
Figure 38. Available Parameter Presets In Parameter Editor
For example, selecting the PMADirect_10G_1_Lane_System_PLL_Custom_cadence preset enables all parameters and ports that the PMA Direct mode requires, with one GTS PMA operating at 10.3125 Gbps.
Table 16.  Preset IP Settings
PMA/FEC Direct Presets Description
FECDirect_10G_1_Lane_System_PLL_FirecodeFEC One FEC Direct GTS lane, operating at 10.3125 Gbps with system PLL clocking mode (Firecode FEC enabled)
FECDirect_16GFC_1_Lane_System_PLL_FirecodeFEC One FEC Direct GTS lane, operating at 14.025 Gbps with system PLL clocking mode (Firecode FEC and custom cadence enabled)
PMADirect_10G_1_Lane_System_PLL_Custom_Cadence One PMA Direct GTS lane, operating at 10.3125 Gbps with system PLL clocking mode (Custom cadence enabled)
PMADirect_17G_1_Lane_PMAClocking One PMA Direct GTS lane, operating at 17.16 Gbps with PMA clocking mode
PMADirect_1G_1_Lane_System_PLL_Custom_Cadence One PMA Direct GTS lane, operating at 1.25 Gbps with system PLL clocking mode (Custom cadence enabled)
PMADirect_2P5G_1_Lane_System_PLL_Custom_Cadence One PMA Direct GTS lane, operating at 3.125 Gbps with system PLL clocking mode (Custom cadence enabled)
PMADirect_40G_4_Lane_PMAClocking Four PMA Direct GTS lanes, operating at 10.3125 Gbps per lane, with PMA clocking mode
PMADirect_6G_2_System_PLL_Custom_Cadence Two PMA Direct GTS lanes, operating at 3.4 Gbps per lane, with system PLL clocking mode (Custom cadence enabled)

Specifying a preset removes any existing parameter values for the IP in the parameter editor. Selecting preset parameters does not prevent you from changing any parameter values to meet the requirements of your design.