Visible to Intel only — GUID: doh1699553438499
Ixiasoft
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
Visible to Intel only — GUID: doh1699553438499
Ixiasoft
3.3.1. Preset IP Parameter Settings
The IP parameter editor provides preset settings for the GTS PMA/FEC Direct PHY Intel FPGA IP. You can specify the preset settings as a starting point for your design. To apply the preset parameters, double-click the preset name, and click Apply as shown in the following figure.
Figure 38. Available Parameter Presets In Parameter Editor
For example, selecting the PMADirect_10G_1_Lane_System_PLL_Custom_cadence preset enables all parameters and ports that the PMA Direct mode requires, with one GTS PMA operating at 10.3125 Gbps.
PMA/FEC Direct Presets | Description |
---|---|
FECDirect_10G_1_Lane_System_PLL_FirecodeFEC | One FEC Direct GTS lane, operating at 10.3125 Gbps with system PLL clocking mode (Firecode FEC enabled) |
FECDirect_16GFC_1_Lane_System_PLL_FirecodeFEC | One FEC Direct GTS lane, operating at 14.025 Gbps with system PLL clocking mode (Firecode FEC and custom cadence enabled) |
PMADirect_10G_1_Lane_System_PLL_Custom_Cadence | One PMA Direct GTS lane, operating at 10.3125 Gbps with system PLL clocking mode (Custom cadence enabled) |
PMADirect_17G_1_Lane_PMAClocking | One PMA Direct GTS lane, operating at 17.16 Gbps with PMA clocking mode |
PMADirect_1G_1_Lane_System_PLL_Custom_Cadence | One PMA Direct GTS lane, operating at 1.25 Gbps with system PLL clocking mode (Custom cadence enabled) |
PMADirect_2P5G_1_Lane_System_PLL_Custom_Cadence | One PMA Direct GTS lane, operating at 3.125 Gbps with system PLL clocking mode (Custom cadence enabled) |
PMADirect_40G_4_Lane_PMAClocking | Four PMA Direct GTS lanes, operating at 10.3125 Gbps per lane, with PMA clocking mode |
PMADirect_6G_2_System_PLL_Custom_Cadence | Two PMA Direct GTS lanes, operating at 3.4 Gbps per lane, with system PLL clocking mode (Custom cadence enabled) |
Specifying a preset removes any existing parameter values for the IP in the parameter editor. Selecting preset parameters does not prevent you from changing any parameter values to meet the requirements of your design.