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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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3.7. Custom Cadence Generation Ports and Logic
When using system PLL clocking mode, you must enable the Custom cadence generation (CCG) ports and logic parameter for the use cases that the Custom Cadence Generation Ports and Logic Use Cases table below describes. Enabling CCG logic ensures that the TX PMA interface FIFO does not overflow due to the over clocking of the datapath when using system PLL clocking mode.
Configuration | Datapath Clocking mode | System PLL Frequency | Enable Custom Cadence Generation (CCG) Ports and Logic |
---|---|---|---|
PMA Direct | PMA | N/A | No |
PMA Direct | System PLL | Equal to PMA parallel clock frequency. No PPM between PMA parallel clock frequency and system PLL frequency. That is, the same reference clock source for PMA and system PLL.30 | No |
PMA Direct | System PLL | Greater than the PMA parallel clock frequency. | Yes |
FEC Direct | System PLL | Equal to the PMA Parallel clock frequency. No PPM between PMA parallel clock frequency and system PLL frequency. That is, the same reference clock source for PMA and system PLL. | No |
FEC Direct | System PLL | Equal to the PMA Parallel clock frequency. PPM between PMA parallel clock frequency and system PLL frequency. That is, different reference clock for PMA and system PLL. | Yes |
FEC Direct | System PLL | Greater than the PMA parallel clock frequency. | Yes |
When you enable Custom cadence generation (CCG) ports and logic, the o_tx_cadence, i_tx_cadence_fast_clk, and i_tx_cadence_slow_clk ports are available in the GTS PMA/FEC Direct PHY Intel FPGA IP. CCG logic uses the i_tx_cadence_fast_clk and i_tx_cadence_slow_clk inputs (does not monitor PMA Interface FIFO status), and generates a o_tx_cadence output signal. You must use o_tx_cadence to assert and de-assert the TX PMA Interface data valid bit. This bit is one of the bits in TX parallel data. Refer to Parallel Data Mapping Information.
Configuration | Enable TX Double Width Transfer | Recommended Connections |
---|---|---|
PMA Direct | Yes |
|
PMA Direct | No |
|
FEC Direct | Yes |
|
30 When using PMA direct with system PLL clocking mode, if the reference clock for PMA and system PLL are from different clock source, then the system PLL frequency cannot be equal to the PMA parallel clock frequency. System PLL frequency must be greater than or equal to the fastest possible TX and RX PMA clock, including PPM.