GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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3.4.2. TX and RX Reference Clock and Clock Output Interface Signals

Table 27.  TX and RX Reference Clock and Clock Output Interface Signals
Signal Name Clocks Domain/Resets Direction Description

o_rx_clkout[(N-1):0]

o_rx_clkout2[(N-1):0)]

o_tx_clkout[(N-1):0]

o_tx_clkout2[(N-1):0]

N/A output Refer to Clock Ports
i_tx_coreclkin[N-1:0] N/A input The FPGA core clock. Drives the write side of the TX FIFO.
i_rx_coreclkin[N-1:0] N/A input The FPGA core clock. Drives the read side of the RX FIFO.
i_tx_pll_refclk_p[N-1:0] N/A input Reference clock for each of the TX PLL. The local reference clock or the regional reference clock pins must be assigned here.
i_rx_cdr_refclk_p[N-1:0] N/A input Every transceiver bank provides a reference clock input for the RX CDR clock block. The local reference clock or the regional reference clock pins must be assigned here.
i_system_pll_clk N/A input To be connected to the GTS System PLL Clock Intel FPGA IP PLL output.
o_tx_pll_locked[N-1:0] asynchronous output TX PLL locked signal for reference clock within the PPM threshold status signal. 1’b1 = locked. 1’b0 = not locked.
o_rx_cdr_divclk N/A output This is the clock used for cases like CPRI to bring the recovered clock to an output pin to be used as reference clock.
o_refclk2core[N-1:0] N/A output Transceiver PLL reference clock that you can route to the FPGA fabric, for example for the HDMI use case.
i_system_pll_lock asynchronous input System PLL locked signal