GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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3.10.4. Accessing Configuration Registers

This section summarizes how to access the configuration registers listed in the GTS PMA/FEC Direct PHY Intel® FPGA IP register map. You can use the detailed information to access the PMA and FEC Direct PHY Soft CSR registers and GTS PMA registers. In this section, the offset address terminology refers to the address of the configuration registers in the GTS PMA/FEC Direct PHY Intel® FPGA IP register map.
Note: The address format in the register map is shown in a byte addressing format. If you are accessing the register through System Console, you can use the byte addressing format. If you are accessing the register with the Nios® V or HPS, you must use word addressing which is the byte address/4.