Visible to Intel only — GUID: yac1666393844172
Ixiasoft
Visible to Intel only — GUID: yac1666393844172
Ixiasoft
2.5.3.4. System PLL Clock for FPGA Core
If the system PLL is not used by the GTS transceiver bank, or it is in a downbonded GTS transceiver bank, it can be used by the FPGA core. In this case, up to three clock outputs (C0, C1, C2) can be generated by the system PLL and fed to the FPGA core.
These clock outputs connect to the FPGA core through the core interface. Each GTS transceiver bank has six core interfaces to the FPGA core; one for PCIe* , one for Ethernet with PTP enabled, and one for each of the four PMA channels in the bank. An unutilized core interface can be used by the system PLL to connect to the FPGA core. The core interfaces for PCIe* and Ethernet with PTP can only accommodate two clock outputs of the system PLL, whereas the others can pass through all three clock outputs.
In the following example, the system PLL outputs of C0 and C1 are fed through the PCIe* core interface as this is one of the two unutilized core interfaces. The four channel core interfaces are being utilized and marked gray in the figure.