Each GTS transceiver bank has one system PLL. The system PLL is the primary clock source for hard IP blocks (Ethernet MAC, PCS, FEC and PCIe) and the core interface which bridges the FPGA core and the GTS transceivers.
The system PLL has one output (C0) to feed those blocks. When you use the system PLL clocking mode, the hard IP blocks are not clocked by the PMA clock. The system PLL can also drive hard IPs in the transceiver banks immediately above it or below it. The system PLL can also be used to clock the PMA direct mode.
You must instantiate and configure the system PLL using the GTS System PLL Clocks Intel FPGA IP. For more information, refer to Implementing the GTS System PLL Clock Intel FPGA IP.
Each system PLL can use either of the local reference clock or regional reference clock in the GTS transceiver bank, or the regional reference clocks coming from other GTS transceiver banks. It can also get the reference clock from four HVIO pins located in the adjacent HVIO bank.
Figure 27. System PLL clock network