GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description

The GTS PMA/FEC Direct PHY Intel FPGA IP example design simulation testbench top-level block diagram is shown in the following figure.
Figure 77. Simulation Testbench Block Diagram for the GTS PMA/FEC Direct PHY Intel Example Design
This section provides the functional description of the example design and the simulation results for both the PMA and FEC direct designs listed in the following table.
Table 68.  Example Design Functional Description
Example Design Option Functional Description
1 x 10.3125G FEC Direct Mode (System PLL Clocking) One NRZ FEC Direct GTS lane operating at 10.3125 Gbps with System PLL clocking mode
4 x 10.3125G PMA Direct Mode (PMA Clocking)

Four NRZ PMA Direct GTS lane operating at 10.3125 Gbps per PMA lane with PMA clocking mode

The testbench program controls the testbench components through the Avalon® memory-mapped interface. For both the PMA and FEC direct example designs, the testwrap block consists of the PRBS generator, PRBS verifier, and TX and RX clock output frequency checkers. There are 2 types of test wrap blocks:
  • PMA test wrap – used in PMA direct configurations.
  • FEC test wrap – used in FEC direct configuration.
The clock sources for the example design are shown in the following table.
Table 69.  Example Design Clock Sources
Example Design Option Clock Source Connections
1 x 10.3125G FEC Direct Mode (System PLL Clocking)
  • 100 MHz for reconfiguration clock
  • 156.25 MHz reference clock for the system PLL
  • 156.25 MHz for the GTS PMA direct channel as TX PLL and RX CDR reference clock
4 x 10.3125G PMA Direct Mode (PMA Clocking)
  • 100 MHz for testbench reset logic, management clock, and reconfiguration clock
  • 156.25 MHz for the GTS PMA direct channel as TX PLL and RX CDR reference clock