PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents

5.2.5. Dynamic Reconfiguration

Because of the asynchronous nature of the PHY, you must perform calibration to achieve timing closure at a high frequency. At a high level, calibration involves reconfiguring input and output delays in the PHY to align data and strobes. With the PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices, you can perform the calibration by using dynamic reconfiguration feature. The dynamic reconfiguration feature allows you to modify these delays by writing to a set of control registers using an Avalon® memory-mapped interface.

Important: When the dynamic reconfiguration feature is enabled in Stratix® 10 devices, the maximum Avalon memory-mapped interface speed is 167 MHz.