PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents

1.2. Features

Features of the PHY Lite for Parallel Interfaces Intel® FPGA IPs:

  • Support interface frequency range of 150 MHz to 1250 MHz (for Agilex™ 5 and Agilex™ 7 M-Series and devices) or 100 MHz to 1200 MHz (for Agilex™ 7 F-Series, Agilex™ 7 I-Series, and older devices).
  • Support input, output, and bidirectional data channels.
  • Support the DQS gating and ungating circuitry for strobe-based interfaces.
  • Support output delays through interpolator.
  • Support dynamic on-chip termination (OCT) control.
  • Support quarter-rate, half-rate, and full-rate mode of the interface clock conversions.
  • Support input, output, and read enable, strobe enable, and OCT enable paths.
  • Support single and double data rates (SDR and DDR) at the I/Os.
  • Support the PHY clock tree.
  • Support dynamically reconfigurable delay chains using the Avalon® memory-mapped interface.
  • Support process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains
    Note: For Stratix® 10, Arria® 10, and Cyclone® 10 GX devices, you can set the non-PVT compensated component of the input delay through Quartus Settings File (.qsf) assignment in the Quartus® Prime software.