PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Calbus Test

If dynamic reconfiguration is enabled, the tester goes to the STATE_TEST_CALBUS before starting write/read tests. At this state, the IOSSM tester reads the output delay on pin 0, adds it by 2 and writes it to the same register and reads it back to confirm the write operation was successful.