PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents

3.2. Functional Description

The PHY Lite for Parallel Interfaces Intel® FPGA IP utilizes the I/O banks in Agilex™ 7 M-Series devices. Each I/O bank has eight I/O lanes with 12 pins in each lane, providing a total of 96 pins per bank. Each bank contains pins that you can use for data and pins that are reserved for strobe, reference clock, and RZQ.
Figure 36. M-Series I/O Bank Structure (Die Top View)This figure shows the I/O bank structure of the M-Series device. The figure shows the view of the die as shown in the Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks and the locations of the SDM and HPS shared I/O banks for each device package.