PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Daisy Chain

The I/O column provides a single physical Avalon® memory-mapped interface. All IPs in the I/O column that require Avalon® memory-mapped interface access the same physical Avalon® memory-mapped interface. The system-level RTL for the column reflects this resource limitation by using a daisy chain to connect all dynamically reconfigurable IPs in an I/O column.

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices exposes a 31-bit Avalon® memory-mapped interface address, followed by a 4-bit interface ID. These bits are only required for the daisy chain arbitration in RTL simulation, so they are not synthesized during compilation. If only one interface is addressed from the IP, it is sufficient to connect these bits as the interface’s ID.

Important: When using multiple PHY Lite for Parallel Interfaces Intel® FPGA IPs, you are required to specify the IP that is directly connected to the Avalon® memory-mapped interface bus master, using the First PHYLite Instance in the Avalon Chain parameter. Do not select the parameter if there is an External Memory Interface IP selected as the first instance in the chain, available in the same column.
Figure 121. Logical RTL View to Physical Column PlacementThis figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices before and after placement.

Notice that all core controllers must go through the arbitration logic that you created in the core logic to connect to an interface on the daisy chain. The end of the daisy chain should have its master output interface tied to 0.

Note: The Fitter rearranges the Avalon® memory-mapped interface address pins during compilation, therefore use the postfit netlist for proper simulation of the merged I/O column instead of prefit netlist.