PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents IOSSM Tester

The IOSSM tester provides an example of how the core logic should drive the AXI4-Lite interface of the Calibration IP to perform read and write operations to the Avalon® memory-mapped calibration addresses. It connects to the AXI4-Lite interface of the Calibration IP through the ports in Table 14. Additional ports of this module are listed in the following table.

Table 32.  IOSSM Tester Ports
Port Type Description
reset_n Input
core_clk Input
iossm_test_start Input Enable the Calbus test
pl_calbus_pass Output Calbus test pass
pl_calbus_fail Output Calbus test fail

This module creates the base address of the Avalon® memory-mapped register that contains the TX delay. The base address is created using the instance ID and lane ID. The full address is derived by adding the offset address of the said register, and it is used as both the write address and read address. This module uses an FSM to go through different stages of read/write operation through AXI4-Lite interface.