PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Write Test

When the tester is in the STATE_TEST_WRITE, it asserts the wrdata_en which drives the pl_wrdata_en. The PHY Lite Interface module delays the enable by one cycle to allow for the preamble. A burst counter counts until reaching TESTER_NUM_BURSTS. While outputting data, we also advance the PRBS to generate new random data. After the burst counter finishes counting, wrdata_finish is asserted. In the write test, handshaking happens in the I/O model. The relevant signals are shown in the following figure.

Figure 33. Write Test Signals