PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Register Map

When you generate the IP, the IP automatically creates the address register map file (addr_map.vh) and the corresponding C header file. It contains the Avalon® memory-mapped interface registers that you can read and write to use the AXI4-Lite IP interface of the Calibration IP.

Since these registers include multiple fields for different settings, only change with a read-modify-write cycle to ensure that other fields in the register remain intact. The address of a register is 24 bits, consisting of an 11-bit base address right padded with 13’b0, and a 13-bit offset address left-padded with 11’b0. The padding is done to make the base address and offset address 24 bits.

The 11-bit base address is configured as:

Base address = {3’b011, 3-bit instance ID, 2-bit atom ID, 3-bit lane ID},

where atom ID is 2’b00 for Byte control. All the reconfigurable PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series settings are in Byte control, i.e., 2’b00.

The offset address for different registers in the address map, as well as bit-field description of the registers, are provided in AXI4-Lite IP Interface Signals table. The Avalon® memory-mapped interface registers are 32-bit wide, but AXI4-Lite IP Interface Signals only shows the relevant bit-fields in the registers as they appear in the automatic generated address map.

As an example, suppose that the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Instance ID is 0 and group 0 is assigned to lane 0. To change the output delay of pin 0, you need to modify the INSTANCE_0_GROUP_0_PIN_00_DDRCRTIMINGCONTROL register.

The base and offset addresses are derived as:

Base address = {3’b011, 3’b000, 2’b00, 3’b000, 13’b0} = 24'h60_0000

Offset address = {11’b0, 0x100} = 24'h00_0100

Full address = Base address + Offset address = 24’h60_0100

Before adjusting any delays with dynamic reconfiguration, set the InternalClocksOn and reset the training. After calibration, reset InternalClocksOn to zero to save power. Follow these steps:
  1. Set InternalClocksOn=1
  2. Reset the training by setting TrainReset from 0 to 1 and back to 0.
  3. Perform calibration.
  4. Set InternalClocksOn=0.
Table 16.  Address Register Map
Register name Offset address (11 bits) Description Bit-field Bit-field Description
INSTANCE_<n>_GROUP_<n>_PIN_00_DDRCRTIMINGCONTROL 0x100 DQ and DQS timing [31:21] TxDqDelay
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_RCVEN 0x114 RcvEn delay for upper nibble [10:0] RxRcvEnPiRank0
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_RCVEN 0x11c RcvEn delay for lower nibble [10:0] RxRcvEnPiRank0
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_DATACONTROL2 0x10c DQ/DQS ODT, DQ sense amp delay and duration upper nibble [31:27] DqsSenseAmpDelay
[26:23] DqSenseAmpDuration
[22:18] DqSenseAmpDelay
[17:14] DqOdtDuration
[13:9] DqOdtDelay
[8:5] DqsOdtDuration
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_DATACONTROL2 0x110 DQ/DQS ODT, DQ sense amp delay and duration lower nibble [31:27] DqsSenseAmpDelay
[26:23] DqSenseAmpDuration
[22:18] DqSenseAmpDelay
[17:14] DqOdtDuration
[13:9] DqOdtDelay
[8:5] DqsOdtDuration
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_DQSSENSEAMPDURATION 0x124 DQS sense amp duration upper nibble [29:26] DqsSenseAmpDuration
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_DQSSENSEAMPDURATION 0x128 ovrd_val for RX path [31] rx_ana_ovrd_val
ovrd_en for RX path [30] rx_ana_ovrd_en
DQS sense amp duration lower nibble [29:26] DqsSenseAmpDuration
INSTANCE_<n>_PHY_LANE_<n>_RXFIFO 0x13c Read enable offset change read valid delay [3:0] read_enable_offset
INSTANCE_<n>_PHY_LANE_<n>_DATATRAINFEEDBACK 0x160 Train reset and training mode [14] TrainReset
[9] RLTrainingMode
INSTANCE_<n>_PHY_LANE_<n>_TRAINFEEDBACK 0x1f4 Train feedback [23:12] DataTrainFeedback_N1
[11:0] DataTrainFeedback_N0
INSTANCE_<n>_PHY_LANE_<n>_DATACONTROL0 0x104 Internal Clocks [11] InternalClocksOn
INSTANCE_<n>_PHY_LANE_<n>_DATACONTROL6 0x130 Vref IO Voltage [29:21] RxDataVrefL
[20:12] RxDataVrefU