PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents

5.2. Functional Description

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices utilizes the I/O subsystem in the Stratix® 10 devices. The I/O subsystem is located in the I/O columns of each Intel FPGA devices. For Stratix® 10 devices, each column consists of I/O banks and IOSSM. The number of I/O banks varies according to device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank. Refer to the Guidelines: Group Pin Placement for more information about the guidelines to implement multiple interfaces in the same bank.

Important: All Stratix® 10 devices have separate LVDS I/O and 3 V I/O banks. The Stratix® 10 GX 10M variant has denser LVDS I/O banks with a slightly different I/O bank structure compared to other Stratix® 10 variants. The PHY Lite for Parallel Interfaces Intel® FPGA IP utilizes only the LVDS I/O banks.
Figure 111.  Stratix® 10 I/O Bank StructureThis figure shows an example of I/O banks in one Stratix® 10 device. The I/O banks availability and locations vary among Stratix® 10 devices.