PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents PHY Lite Interface

This module models the core logic. Apart from the ports listed in PHY Lite IP Instance and Tester Port Connections table, additional ports for this module are shown in the following table.

Table 30.  PHY Lite Interface Module Ports
Port Type Description
reset_n Input
core_clk Input
repeat_count Input Tester repeat count
pl_wrdata_en Input Write enable from core
pl_rddata_en Input Read enable from core
pl_rddata_pass Output Read pass
pl_rddata_fail Output Read fail

In the write test, this module provides the enable signals for data and strobe, the strobe pattern, and random data generated by the PRBS channel.

In the read test, it provides the read enable signal from core, receives the data and strobe and performs a check using a PRBS channel, and provides the corresponding read pass or read fail signal. There is also reframing logic to find the frame offset in LINK mode.