PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents

3.2.2. Dynamic Reconfiguration

If you enable dynamic reconfiguration, you can use an Avalon® memory-mapped interface to reconfigure the input and output delays in the PHY and calibrate the delays. Through calibration, you can optimize the delay settings to maximize the capture window. You can access the Avalon® memory-mapped interface through the Calibration Intel® FPGA IP. The IP provides an ARM AMBA* AXI4 Lite Interface. You can connect the Calibration IP to two PHY Lite for Parallel Interfaces IP instances in an I/O bank.

For differential data, program the output delay settings for both pins in a differential pair, and the input settings only for the even pin.

You can only reset the PHY by enabling dynamic reconfiguration and writing to the TrainReset bit. The reset port in PHY Lite for Parallel Interfaces IP is only for power-up reset.

Figure 44. Connection of the Calibration IP to the PHY Lite for Parallel Interfaces IP