PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Read Test

The receiver is tested using one cycle of preamble and 0x1, 0x0 strobe pattern. PHYLITE_READ_LATENCY must exactly match the internal rddata_en to RcvEn latency of the PHY. The phase shift of RcvEn may need to be adjusted to maximize margin. This test is shown in the following figure.

Figure 34. Read Test Using One Cycle of PreambleThis figure shows the read test performed using one cycle of preamble.
Figure 35. Handshaking Signals in Read TestThis figure shows Handshaking signals in the read test.