PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Pin Placement Restrictions

Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel® FPGA IP group pins:

  1. Assign each lane to only one group. Each group is either mapped to one lane (x8 mode) or two lanes (x16 mode). When using x16 DQS tree, the first lane should be an even lane.
  2. If using termination with calibration, reserve pin 38 or 62 for RZQ. RZQ is a 240 ohm resistor that you attach it to a specific pin as an impedance reference to calibrate driving and termination impedances to avoid signal reflection. One RZQ group can support up to two different output terminations and one input termination. RZQ pin cannot be used as data pin.
  3. No input or bidirectional pins can be placed in the same lane as RZQ.
  4. Place differential data on two adjacent pins. The first pin should be an even pin. The following shows two differential data pins placed on pins 2 and 12, and occupying 4 pins in total. This example uses an x16 DQS tree since the data pins span over two lanes.
  5. Differential refclk is not supported in the same lane as PHY Lite IP for the LVSTL I/O standard.
  6. For both auto and manual pin placements, ensure that the ref_clk pins are reserved only in any of the following eight pins:
    • Pins 34, 35 (Lane 2)
    • Pins 36, 37 (Lane 3)
    • Pins 58, 59 (Lane 4)
    • Pins 60, 61 (Lane 5)
  7. PHY Lite IP instances in different I/O banks must be connected to different Calibration IPs.
  8. PHY Lite IP instances in the same I/O bank will be connected to the same Calibration IP, but different Instance ID must be assigned in the IP Parameter Editor to differentiate the base address of the instances (Rev B only).
  9. In the input-only pins with I/O standard, SSTL-12 or HSTL-12, toggle rddata_en to benefit from On-Die Termination (ODT) rotation. If RX is enabled 100% of the time (if rddata_en is not toggled), only 32 data pins are allowed.

    Rotation happens when rddata_en goes low. However, if the receiving data in bursts and the burst sizes are not equal, the maximum imbalance should be 40% to 60% to get credit for the first row in On-Die Termination (ODT).

    To support 100% Activity Factor (AF), toggle rddata_en at least 80% of the time with a maximum imbalance of 40% to 60%.

Figure 45. Differential Data Pin Placement
Figure 46. On-Die Termination (ODT) Rotation
Table 54.  On-Die Termination (ODT)
Case Maximum Input Pins
90%<AF≤100% 32
80%<AF≤90% 38
70%<AF≤80% 48
60%<AF≤70% 58
0%<AF≤60% 96