PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Generating the Synthesis Design Example

The make_qii_design.tcl generates a synthesizable hardware design example and an Quartus® Prime project, ready for compilation.

To generate synthesizable design example, run the following script at the end of IP generation:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following script:
quartus_sh -t make_qii_design.tcl [device_name]

This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile this project using the Quartus® Prime software.

Figure 105. High-Level View of the Synthesis Design Example with One Group