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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: fsv1606745371362
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4.2.4.2.1. Control Registers Addresses
For the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series devices, the address register map is automatically generated when the IP is generated. The address register map can be obtained in the ip/ed_synth/<PHY Lite IP folder>/altera_arch_fm_xxx/synth/addr_map.vh.
Feature | Bit | Description |
---|---|---|
Pin Output Delay | [26:24] | The Avalon® controller calibration bus base address. Value is fixed to 3’h3. |
[23:21] | Reserved with value 3’h0. | |
[20:13] | The lane address of an interface. | |
[12:8] | The address for the physical location of a pin within a lane. | |
[7:0] | Reserved with value 8’d0 | |
Pin Input Delay | [26:24] | The Avalon® controller calibration bus base address. Value is fixed to 3’h3. |
[23:21] | Reserved with value 3’h0. | |
[20:13] | The lane address of an interface. | |
[12:9] | Reserved with value 4’hC. | |
[8:7] | DQ pin sets to access.
|
|
[6:4] | Specific DQ pin to access.
|
|
[3:0] | Reserved with value 4’h0. | |
Strobe Input Delay | [26:24] | The Avalon® controller calibration bus base address. Value is fixed to 3’h3. |
[23:21] | Reserved with value 3’h0. | |
[20:13] | The lane address of an interface. | |
[12:0] | Reserved with value 13'h18E0. | |
Strobe Enable Phase | [26:24] | The Avalon® controller calibration bus base address. Value is fixed to 3’h3. |
[23:21] | Reserved with value 3’h0. | |
[20:13] | The lane address of an interface. | |
[12:0] | Reserved with value 13'h18F0. | |
Strobe Enable Delay | [26:24] | The Avalon® controller calibration bus base address. Value is fixed to 3’h3. |
[23:21] | Reserved with value 3’h0. | |
[20:13] | The lane address of an interface. | |
[12:0] | Reserved with value 13'h1808. | |
Read Valid Delay | [26:24] | The Avalon® controller calibration bus base address. Value is fixed to 3’h3. |
[23:21] | Reserved with value 3’h0. | |
[20:13] | The lane address of an interface. | |
[12:0] | Reserved with value 13'h180C. |