PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents DQS Trees

The PHY Lite for Parallel Interfaces IP supports two DQS trees, namely an x8 tree that spans over one lane and an x16 tree that spans over two adjacent lanes, as described in the following table.

Table 22.  DQS Trees in Agilex™ 5 E-Series Devices
DQS tree Lane(s) used Group size Strobe pins
x8 Any lane 1 - 10 Pin 4, 5





1 - 22 Pin 4, 5 of the even lane

For single-ended strobe, only pin 4 is used as DQS. The remaining strobe pin (pin 5) cannot be used as data.