PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents I/O Model

This module models the I/O pins. The write path is running a state machine to implement the preamble mode, explained in more details in Read test section. In the I/O model, mem_clk is generated from the core clock. Apart from the ports listed in Table 28 table, additional ports for this module are shown in the following table.

Table 31.  I/O Model Module Ports
Port Type Description
reset_n Input
core_clk Input
repeat_count Input Tester repeat count
io_wrdata_en Input Write enable from tester
io_rddata_en Input Read enable from tester
io_rddata_pass Output Read pass
io_rddata_fail Output Read fail