PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Mixed Pin Configurations

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices allows a mixture of pin configurations, provided that general pin restrictions are followed. For instance, the following table and figure show a mixed pin configuration, using the same scenario of a single-ended ref_clk reserved on pin 36 (Lane 3) and using differential strobe pins. The total number of DQ pins depends on the mixed pin configuration setting.

Table 24.  Example of Mixed Pin Configuration Settings
Group Pin Type Pin Width DDR/SDR Pin Configuration
0 Bidirectional 10 DDR Single-ended
1 Input 10 DDR Single-ended
2 Output 11 DDR Differential
3 Output 8 SDR Single-ended
4 Bidirectional 9 DDR Single-ended
5 Bidirectional 11 DDR Differential
Figure 28. Example of Mixed Pin Configuration