PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Clock and Reset Interface Signals

The following table provides the clock and reset interface signals in PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices.

Table 18.  Clock and Reset Interface Signals
Signal Name Direction Width Description
ref_clk Input 1 Reference clock for the PLL. The reference clock must be synchronous with group_strobe_in to ensure the dqs_enable signal is in-sync with group_strobe_in.
reset_n Input 1 Resets the interface. This is only for power-up reset. Reset of the PHY can only be achieved by enabling dynamic reconfiguration and writing to the TrainReset bit.
interface_locked Output 1

The interface_locked signal from PHY Lite for Parallel Interfaces Agilex™ FPGA IP to the core logic. This signal indicates that the PLL and PHY circuitry are locked.

Data transfer should start after the assertion of this signal and control signals should be kept at zero before interface_locked is asserted.

core_clk_out Output 1

Use this core clock in the core-to-periphery transfer of soft logic data and control signals.

The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter.

rzq Input 1 This interface will be visible if on-chip termination (OCT) with calibration is selected in the IP Parameter Editor GUI.