PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents

2.2. Functional Description

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices utilizes the IO96 I/O banks in Agilex™ 5 E-Series devices. In general, each IO96 I/O bank has eight I/O lanes with 12 pins in each lane, providing a total of 96 pins per bank. Each bank contains pins that you can use for data and pins that are reserved for single-ended or differential strobe, reference clock, and RZQ. Some Agilex™ 5 E-Series packages may have partially bonded out I/O banks. The PHY Lite IP can still be used in these partially bonded out I/O banks, but with fewer than 96 pins available. For details about supported I/O banks, refer to the Agilex™ 5 E-Series Device Handbook. The following figure shows the Agilex™ 5 E-Series HSIO Bank Structure (Die Top View).

Figure 1.  Agilex™ 5 HSIO Bank Structure (Die Top View)This figure shows the HSIO bank structure of the Agilex™ 5 device. The figure shows the view of the die as shown in the Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different device packages have different number of HSIO banks. Refer to the device pin-out files for available HSIO banks and the locations of the HPS shared HSIO banks for each device package.