PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Run the Simulation Design Example Without Dynamic Reconfiguration

Follow these steps to compile and simulate the design:

  1. Change the working directory to <Example Design>\sim\ed_sim\<Simulator>.
  2. Run the simulation script for the simulator of your choice. Refer to the following table.
Table 27.  Steps to Run Simulation Script for Different Simulators
Simulator Working Directory Steps
Questasim <Example Design>/sim/ed_sim/mentor
  • vsim
  • do msim_setup.tcl
  • ld_debug
  • Add desired signals into the waveform window
  • run -all
VCS <Example Design>/sim/ed_sim/synopsys/vcs sh
VCSMX <Example Design>/sim/ed_sim/synopsys/vcsmx sh
Xcelium <Example Design>/sim/ed_sim/xcelium sh