PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents

4.2.4. Dynamic Reconfiguration

You must perform calibration to achieve timing closure at a high frequency because of the asynchronous nature of the PHY. At a high level, calibration involves reconfiguring input and output delays in the PHY to align data and strobes. With the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series devices, you can perform calibration using the dynamic reconfiguration feature. The dynamic reconfiguration feature allows you to modify the input and output delays by writing to a set of control registers using an Avalon® memory-mapped interface.

Note: Follow the guidelines described in the Dynamic Reconfiguration Guidelines section when generating your own dynamic reconfiguration controller.