PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/01/2024
Document Table of Contents Input Path

The simplified input path of the IP consists of the pipeline registers, receiver FIFO, shift registers, and phase shift logics.

Figure 7. Simplified Input PathThis figure shows the input path for the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices.
Table 8.  Components in the Simplified Input Path of the PHY Lite for Parallel Interfaces Intel® FPGA IP
Component Description
Pipeline Registers Represent pipeline stages in the input path
2x RX FIFOs Perform 2:1 rate conversion on the RX data
  • At positive edge of strobe_in signal
  • At negative edge of strobe_in signal
Shift Registers Perform the following functions:
  • Delay the RcvEn signal in VCO cycle increments
  • The read_enable_offset shift register delays the rdata_valid signal
Phase Shift Logics Perform the following functions:
  • Delay RcvEn signal in 1/128 VCO cycle increments
  • Delay RxDqsNDelayPi and RxDqsPDelayPi signals
There are five types of delay in the input path. The following table describes the reconfigurable input path delays for the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series.
Table 9.  Types of Delay in Input Path
Delay Type Description
Inherent latency Static Captured in pipeline stages from the assertion of group_<n>_rdata_en signal in core until internal signal, RcvEn, is asserted.
RcvEn delay (internal signal generated from input signal rdata_en) Dynamic You can reconfigure these delays in the control registers. You can program the RcvEn delay statically or dynamically through the Additional Receiver Enable Latency settings in the IP Parameter Editor.
Positive-edge strobe_in delay
Negative-edge strobe_in delay
rdata_valid delay
Table 10.  Input Path Reconfigurable Delays DescriptionThis table lists all the reconfigurable input path delays for the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices.
Feature Description Bit-field Description Min Max
  • RcvEn delay
  • There are two RxRcvEnPiRank0 registers per lane. One controls the lower nibble (6 pins) and the other controls the upper nibble of the lane.
  • In PHY Lite IP, the nibbles cannot be used independently. Both control signals must be programmed to the same value.
  • Changing these delays requires the ODT and SA settings to be adjusted according to Settings for DQ/DQS ODT/SA Delays table.
Bit 10 to bit 7 represents integer number of VCO clock cycles to delay RcvEn signal. 0 15
RxRcvEnPiRank0[6:0] Bit 6 to bit 0 represents additional phase shift in RcvEn signal measured in 1/128 of VCO clock period. 0 127
  • strobe_in delay
  • There are two RxDqsNDelayPi and RxDqsPDelayPi for each pin. Each pin receives a copy of the DQS and can phase-shift each edge of the DQS independently of other pins.
  • Usually both edges should be set to the same delay value, but different values can be used to correct uneven duty cycle. The effective range of this delay setting is up to 1 VCO clock cycle.
Phase shift in the negative edge of the DQS for each pin measured in 1/128 of VCO clock period. 0 127
RxDqsPDelayPi[6:0] Phase shift in the positive edge of the DQS for each pin measured in 1/128 of VCO clock period. 0 127
  • rdata_valid delay
  • An adjustable setting that changes the delay before starting to read from the RX FIFO, effectively delaying the rdata_valid signal.
  • This delay setting is downstream from the integer portion of the RcvEn delay, so any additional RcvEn delay applies to the rdata_valid signal as well. Refer to Allowed Values for read_enable_offset Based on RcvEn Coarse Delay for allowed delay values based on RcvEn delay.
Delay before reading from the RX FIFO measured in number of PHY clock cycles. 0 15
Figure 8. Input OperationThis figure shows the input operation for the PHY Lite for Parallel Interfaces Agilex™ 5 E-Series FPGA IP / PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices.

The preceding figure shows an example of RX data transfer in QR DDR. In this illustration, the data_to_core output signal to the FPGA fabric for each pin is 8 bits wide. The PHY Lite IP uses DDR4 preamble settings, expecting one cycle of preamble by default.

Setting the parameter Capture strobe phaseshift to 90 degrees in the IP Parameter Editor, as shown in the following figure, causes the PHY Lite IP to accept edge-aligned input data, data_in, with respect to the input strobe signal, strobe_in.

Figure 9. Default Input Path Settings

The inherent latency in the RcvEn path measured from the assertion of read enable in the core until the RcvEn signal (internal) is asserted is presented in the following table. The parameter Additional receiver enable latency is added to the inherent latency. The maximum allowed value for this parameter is shown in the third column in the following table.

Table 11.  RcvEn Path Inherent Latency and Maximum Additional Rcven Latency
I/O Frequency (MHz) Inherent Latency in the RcvEn Path (# of IO Clock Cycles) Maximum Additional RcvEn Latency
600 - 1250 27 15
300 - 600 13 7
150 - 300 7 3

To ensure that the IP uses only clock edges associated with valid input data, gate the receiver off when PHY Lite for Parallel Interfaces IP is not accepting input data. If there are extra toggling signals or noise on the DQS port, use a refined version of the received strobe. The gating signal, RcvEn (receiver enable), is derived internally from the rdata_en signal. Use the RcvEn signal to ungate the DQS gate window by asserting RcvEn up to one cycle before the first rising edge of DQS, as shown in the following figure. You require no more than one cycle preamble in the strobe signal.

Figure 10. Ungating DQS Gate WindowThis figure shows the ungating of the DQS window by internally asserting the RcvEn signal.

The process of shutting off the DQS gate happens automatically after the last burst ends.

In the input path, program the on die termination (ODT) and sense amplifier (SA) when you dynamically reconfigure the RcvEn delay.

To save power in idle mode, gate off the ODT and SA using two enable signals tapped from the same shift register as RcvEn.

Whenever you reconfigure the RcvEn delay, reconfigure the following ODT and SA settings to ensure that all parts of the receiver circuitry turns on at the correct time:
  • DqsSenseAmpDelay
  • DqsSenseAmpDuration
  • DqSenseAmpDuration
  • DqSenseAmpDelay
  • DqOdtDuration
  • DqOdtDelay
  • DqsOdtDuration
  • DqsOdtDelay
Adjust these settings for both upper and lower nibbles in the lane according to the following table.
Table 12.  Settings for DQ/DQS ODT/SA DelaysThis table lists the settings adjustments for both the upper and lower nibbles in the lane.
RxRcvEnPi[10:7]>>Gear42 DqsOdtDelay DqOdtDelays Dq/Dqs SenseAmpDelay
0 2 3 3
1 3 4 4
2 4 5 5
3 5 6 6
4 6 7 7
5 7 8 8
6 8 9 9
7 9 10 10

When changing the RcvEn coarse delay or RxRcvEnPiRank0[10:7], Intel recommends that you update read_enable_offset to avoid receiving misaligned data in the core. The small values of read_enable_offset can cause RX FIFO underflow, while large values may cause an overflow.

Table 13.  Allowed Values For read_enable_offset Based on RcvEn Coarse Delay
RxRcvEnPiRank0[10:7] Allowed values for read_enable_offset
0, 1, 4, 5, 8, 9, 12, 13 3, 5, 7, 9, 11
2, 3, 6, 7, 10, 11, 14, 15 4, 6, 8, 10, 12
2 This value is the shifted value of RxRcvEnPi[10:7] and Gear4 value is always 1.