2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
126.96.36.199. Use Synchronous Memory Blocks 188.8.131.52. Avoid Unsupported Reset and Control Conditions 184.108.40.206. Check Read-During-Write Behavior 220.127.116.11. Controlling RAM Inference and Implementation 18.104.22.168. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 22.214.171.124. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 126.96.36.199. Simple Dual-Port, Dual-Clock Synchronous RAM 188.8.131.52. True Dual-Port Synchronous RAM 184.108.40.206. Mixed-Width Dual-Port RAM 220.127.116.11. RAM with Byte-Enable Signals 18.104.22.168. Specifying Initial Memory Contents at Power-Up
22.214.171.124. If Performance is Important, Optimize for Speed 126.96.36.199. Use Separate CRC Blocks Instead of Cascaded Stages 188.8.131.52. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 184.108.40.206. Take Advantage of Latency if Available 220.127.116.11. Save Power by Disabling CRC Blocks When Not in Use 18.104.22.168. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
22.214.171.124. VHDL State Machines
To ensure proper recognition and inference of VHDL state machines, represent the different states with enumerated types, and use the corresponding types to make state assignments.
This implementation makes the state machine easier to read, and reduces the risk of errors during coding. If your RTL does not represent states with an enumerated type, Intel® Quartus® Prime synthesis (and other synthesis tools) do not recognize the state machine. Instead, synthesis implements the state machine as regular logic gates and registers. Consequently, and the state machine does not appear in the state machine list of the Intel® Quartus® Prime Compilation Report, Analysis & Synthesis section. Moreover, Intel® Quartus® Prime synthesis does not perform any of the optimizations that are specific to state machines.
VHDL State Machine Coding Example
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