2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
184.108.40.206. Use Synchronous Memory Blocks 220.127.116.11. Avoid Unsupported Reset and Control Conditions 18.104.22.168. Check Read-During-Write Behavior 22.214.171.124. Controlling RAM Inference and Implementation 126.96.36.199. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 188.8.131.52. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 184.108.40.206. Simple Dual-Port, Dual-Clock Synchronous RAM 220.127.116.11. True Dual-Port Synchronous RAM 18.104.22.168. Mixed-Width Dual-Port RAM 22.214.171.124. RAM with Byte-Enable Signals 126.96.36.199. Specifying Initial Memory Contents at Power-Up
188.8.131.52. If Performance is Important, Optimize for Speed 184.108.40.206. Use Separate CRC Blocks Instead of Cascaded Stages 220.127.116.11. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 18.104.22.168. Take Advantage of Latency if Available 22.214.171.124. Save Power by Disabling CRC Blocks When Not in Use 126.96.36.199. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
188.8.131.52. Optimizing Critical Timing Paths
To close timing in high speed designs, review paths with the largest timing failures. Correcting a single, large timing failure can result in a very significant timing improvement.
Review the register placement and routing paths by clicking Tools > Chip Planner. Large timing failures on high fan-out control signals can be caused by any of the following conditions:
- Sub-optimal use of global networks
- Signals that traverse the chip on local routing without pipelining
- Failure to correct high fan-out by register duplication
For high-speed and high-bandwidth designs, optimize speed by reducing bus width and wire usage. To reduce wire usage, move the data as little as possible. For example, if a block of logic functions on a few bits of a word, store inactive bits in a FIFO or memory. Memory is cheaper and denser than registers, and reduces wire usage.
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