Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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3.2.1.2. Synchronizer Summary Report

The Synchronizer Summary lists the synchronization register chains detected in the design depending on the Synchronizer Identification setting.

The Source Node is the register or input port that is the source of the asynchronous transfer. The Synchronization Node is the first register of the synchronization chain. The Source Clock is the clock domain of the source node, and the Synchronization Clock is the clock domain of the synchronizer chain.

This summary reports the calculated Worst-Case MTBF, if available, and the Typical MTBF, for each appropriately identified synchronization register chain that meets its timing requirement.