Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
Document Table of Contents Optimizing for Timing Closure

To achieve timing closure for your design, you can enable compilation settings in the Intel® Quartus® Prime software, or you can directly modify your timing constraints.

Compilation Settings for Timing Closure

Note: Changes in project settings can significantly increase compilation time. You can view the performance gain versus runtime cost by reviewing the Fitter messages after design processing.
Table 1.  Compilation Settings that Impact Timing Closure
Setting Location Effect on Timing Closure
Perform Physical Synthesis for Combinational logic for Performance Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) If enabled, the Netlist Optimization report panel identifies logic that physical synthesis can modify. You can use this information to modify the design so that the associated optimization can be turned off to save compile time.
Allow Register Duplication Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)

This technique is most useful where registers have high fan-out, or where the fan-out is in physically distant areas of the device.

Review the netlist optimizations report and consider manually duplicating registers automatically added by physical synthesis. You can also locate the original and duplicate registers in the Chip Planner. Compare their locations, and if the fan-out is improved, modify the code and turn off register duplication to save compile time.

Prevent Register Retiming Assignments > Settings > Compiler Settings

Useful if some combinatorial paths between registers exceed the timing goal while other paths fall short.

If a design is already heavily pipelined, register retiming is less likely to provide significant performance gains, since there should not be significantly unbalanced levels of logic across pipeline stages.

Guidelines for Optimizing Timing Closure using Timing Constraints

Appropriate timing constraints are essential to achieving timing closure. Use the following general guidelines in applying timing constraints:

  • Apply multicycle constraints in your design wherever single-cycle timing analysis is not necessary.
  • Apply False Path constraints to all asynchronous clock domain crossings or resets in the design. This technique prevents overconstraining and the Fitter focuses only on critical paths to reduce compile time. However, overconstraining timing critical clock domains can sometimes provide better timing results and lower compile times than physical synthesis.
  • Overconstrain rather than using physical synthesis when the slack improvement from physical synthesis is near zero. Overconstrain the frequency requirement on timing critical clock domains by using setup uncertainty.
  • When evaluating the effect of constraint changes on performance and runtime, compile the design with at least three different seeds to determine the average performance and runtime effects. Different constraint combinations produce various results. Three samples or more establish a performance trend. Modify your constraints based on performance improvement or decline.
  • Leave settings at the default value whenever possible. Increasing performance constraints can increase the compile time significantly. While those increases may be necessary to close timing on a design, using the default settings whenever possible minimizes compile time.