Visible to Intel only — GUID: mwh1409959594111
Src Path: Ixiasoft
2.1. Using Provided HDL Templates
2.2. Instantiating IP Cores in HDL
2.3. Inferring Multipliers and DSP Functions
2.4. Inferring Memory Functions from HDL Code
2.5. Register and Latch Coding Guidelines
2.6. General Coding Guidelines
2.7. Designing with Low-Level Primitives
2.8. Recommended HDL Coding Styles Revision History
2.4.1.1. Use Synchronous Memory Blocks
2.4.1.2. Avoid Unsupported Reset and Control Conditions
2.4.1.3. Check Read-During-Write Behavior
2.4.1.4. Controlling RAM Inference and Implementation
2.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior
2.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior
2.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM
2.4.1.8. True Dual-Port Synchronous RAM
2.4.1.9. Mixed-Width Dual-Port RAM
2.4.1.10. RAM with Byte-Enable Signals
2.4.1.11. Specifying Initial Memory Contents at Power-Up
2.4.3.1. Simple Shift Register
2.4.3.2. Shift Register with Evenly Spaced Taps
Verilog HDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps=mwh1409959594111__example_C9B3E02147AF4E9C841A785B0923503E
VHDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps=mwh1409959594111__example_6A8646FEC75946A2B0ECC52049161DD6
2.6.6.1. If Performance is Important, Optimize for Speed
2.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages
2.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge
2.6.6.4. Take Advantage of Latency if Available
2.6.6.5. Save Power by Disabling CRC Blocks When Not in Use
2.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer
3.4.2. Force the Identification of Synchronization Registers
3.4.3. Set the Synchronizer Data Toggle Rate
3.4.4. Optimize Metastability During Fitting
3.4.5. Increase the Length of Synchronizers to Protect and Optimize
3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit
3.4.7. Increase the Number of Stages Used in Synchronizers
3.4.8. Select a Faster Speed Grade Device
Visible to Intel only — GUID: mwh1409959594111
Src Path: Ixiasoft
2.4.3.2. Shift Register with Evenly Spaced Taps
The following examples show a Verilog HDL and VHDL 8-bit wide, 64-bit long shift register (W > 1 and M = 64) with evenly spaced taps at 15, 31, and 47.
The synthesis software implements this function in a single ALTSHIFT_TAPS IP core and maps it to RAM in supported devices, which is allowed placement in dedicated RAM blocks or MLAB memory.
Verilog HDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps
module top (clk, shift, sr_in, sr_out, sr_tap_one, sr_tap_two,
sr_tap_three );
input clk, shift;
input [7:0] sr_in;
output [7:0] sr_tap_one, sr_tap_two, sr_tap_three, sr_out;
reg [7:0] sr [64:0];
integer n;
always @ (posedge clk)
begin
if (shift == 1'b1)
begin
for (n = 64; n>0; n = n-1)
begin
sr[n] <= sr[n-1];
end
sr[0] <= sr_in;
end
end
assign sr_tap_one = sr[16];
assign sr_tap_two = sr[32];
assign sr_tap_three = sr[48];
assign sr_out = sr[64];
endmoduleVHDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY shift_8x64_taps IS
PORT (
clk: IN STD_LOGIC;
shift: IN STD_LOGIC;
sr_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sr_tap_one: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sr_tap_two : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sr_tap_three: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sr_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END shift_8x64_taps;
ARCHITECTURE arch OF shift_8x64_taps IS
SUBTYPE sr_width IS STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE sr_length IS ARRAY (63 DOWNTO 0) OF sr_width;
SIGNAL sr: sr_length;
BEGIN
PROCESS (clk)
BEGIN
IF (rising_edge(clk)) THEN
IF (shift = '1') THEN
sr(63 DOWNTO 1) <= sr(62 DOWNTO 0);
sr(0) <= sr_in;
END IF;
END IF;
END PROCESS;
sr_tap_one <= sr(15);
sr_tap_two <= sr(31);
sr_tap_three <= sr(47);
sr_out <= sr(63);
END arch;