Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
Public
Download
Document Table of Contents

2.4.3.2. Shift Register with Evenly Spaced Taps

The following examples show a Verilog HDL and VHDL 8-bit wide, 64-bit long shift register (W > 1 and M = 64) with evenly spaced taps at 15, 31, and 47.

The synthesis software implements this function in a single ALTSHIFT_TAPS IP core and maps it to RAM in supported devices, which is allowed placement in dedicated RAM blocks or MLAB memory.

Verilog HDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps

module top (clk, shift, sr_in, sr_out, sr_tap_one, sr_tap_two,
				sr_tap_three );
	input clk, shift;
	input [7:0] sr_in;
	output [7:0] sr_tap_one, sr_tap_two, sr_tap_three, sr_out;
	reg [7:0] sr [64:0];
	integer n;
	always @ (posedge clk)
		begin
		if (shift == 1'b1)
			begin
			for (n = 64; n>0; n = n-1)
				begin
				sr[n] <= sr[n-1];
				end
			sr[0] <= sr_in;
		end
	end
	assign sr_tap_one = sr[16];
	assign sr_tap_two = sr[32];
	assign sr_tap_three = sr[48];
	assign sr_out = sr[64];
endmodule

VHDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY shift_8x64_taps IS
	PORT (
		clk: IN STD_LOGIC;
		shift: IN STD_LOGIC;
		sr_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		sr_tap_one: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		sr_tap_two : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		sr_tap_three: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		sr_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END shift_8x64_taps;

ARCHITECTURE arch OF shift_8x64_taps IS
	SUBTYPE sr_width IS STD_LOGIC_VECTOR(7 DOWNTO 0);
	TYPE sr_length IS ARRAY (63 DOWNTO 0) OF sr_width;
	SIGNAL sr: sr_length;
BEGIN
	PROCESS (clk)
	BEGIN
		IF (rising_edge(clk)) THEN
			IF (shift = '1') THEN
				sr(63 DOWNTO 1) <= sr(62 DOWNTO 0);
				sr(0) <= sr_in;
			END IF;
		END IF;
	END PROCESS;
	sr_tap_one <= sr(15);
	sr_tap_two <= sr(31);
	sr_tap_three <= sr(47);
	sr_out <= sr(63);
END arch;