Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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3.3. MTBF Optimization

In addition to reporting synchronization register chains and MTBF values found in the design, the Intel® Quartus® Prime software can also protect these registers from optimizations that might negatively impact MTBF and can optimize the register placement and routing if the MTBF is too low.

Synchronization register chains must first be explicitly identified as synchronizers. Intel recommends that you set Synchronizer Identification to Forced If Asynchronous for all registers that are part of a synchronizer chain.

Optimization algorithms, such as register duplication and logic retiming in physical synthesis, are not performed on identified synchronization registers. The Fitter protects the number of synchronization registers specified by the Synchronizer Register Chain Length option.

In addition, the Fitter optimizes identified synchronizers for improved MTBF by placing and routing the registers to increase their output setup slack values. Adding slack in the synchronizer chain increases the available settling time for a potentially metastable signal, which improves the chance that the signal resolves to a known value, and exponentially increases the design MTBF. The Fitter optimizes the number of synchronization registers specified by the Synchronizer Register Chain Length option.

Metastability optimization is on by default. To view or change the Optimize Design for Metastability option, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter). To turn the optimization on or off with Tcl, use the following command:

set_global_assignment -name OPTIMIZE_FOR_METASTABILITY <ON|OFF>