18.104.22.168.1. Binary Multiplexers
Device families featuring 6-input look up tables (LUTs) are perfectly suited for 4:1 multiplexer building blocks (4 data and 2 select inputs). The extended input mode facilitates implementing 8:1 blocks, and the fractured mode handles residual 2:1 multiplexer pairs.
For device families using 4-input LUTs, such as the Cyclone® series and Stratix® series devices, Intel® Quartus® Prime implements the 4:1 binary multiplexer efficiently by using two 4-input LUTs. Intel® Quartus® Prime decomposes larger binary multiplexers into 4:1 multiplexer blocks, possibly with a residual 2:1 multiplexer at the head.
Verilog HDL Binary-Encoded Multiplexers
case (sel) 2'b00: z = a; 2'b01: z = b; 2'b10: z = c; 2'b11: z = d; endcase