Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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2.4. Inferring Memory Functions from HDL Code

The following coding recommendations provide portable examples of generic HDL code targeting dedicated Intel FPGA memory IP cores. However, if you want to use some of the advanced memory features in Intel FPGA devices, consider using the IP core directly so that you can customize the ports and parameters easily.

You can also use the Intel® Quartus® Prime templates provided in the Intel® Quartus® Prime software as a starting point. Most of these designs can also be found on the Design Examples page on the Altera website.

Table 2.   Intel Memory HDL Language Templates

Language

Full Design Name

VHDL

Single-Port RAM

Single-Port RAM with Initial Contents

Simple Dual-Port RAM (single clock)

Simple Dual-Port RAM (dual clock)

True Dual-Port RAM (single clock)

True Dual-Port RAM (dual clock)

Mixed-Width RAM

Mixed-Width True Dual-Port RAM

Byte-Enabled Simple Dual-Port RAM

Byte-Enabled True Dual-Port RAM

Single-Port ROM

Dual-Port ROM

Verilog HDL

Single-Port RAM

Single-Port RAM with Initial Contents

Simple Dual-Port RAM (single clock)

Simple Dual-Port RAM (dual clock)

True Dual-Port RAM (single clock)

True Dual-Port RAM (dual clock)

Single-Port ROM

Dual-Port ROM

SystemVerilog

Mixed-Width Port RAM

Mixed-Width True Dual-Port RAM

Mixed-Width True Dual-Port RAM (new data on same port read during write)

Byte-Enabled Simple Dual Port RAM

Byte-Enabled True Dual-Port RAM