ID 683323
Date 9/24/2018
Public

## 2.6.8. Counter HDL Guidelines

The Intel® Quartus® Prime synthesis engine implements counters in HDL code as an adder followed by registers, and makes available register control signals such as enable (ena), synchronous clear (sclr), and synchronous load (sload). For best area utilization, ensure that the up and down control or controls are expressed in terms of one addition operator, instead of two separate addition operators.
If you use the following coding style, your synthesis engine may implement two separate carry chains for addition:
out <= count_up ? out + 1 : out - 1;

For simple designs, the synthesis engine identifies this coding style and optimizes the logic. However, in complex designs, or designs with preserve pragmas, the Compiler cannot optimize all logic, so more careful coding becomes necessary.

The following coding style requires only one adder along with some other logic:
out <= out + (count_up ? 1 : -1);

This style makes more efficient use of resources and area, since it uses only one carry chain adder, and the –1 constant logic is implemented in the LUT before the adder.