2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
184.108.40.206. Use Synchronous Memory Blocks 220.127.116.11. Avoid Unsupported Reset and Control Conditions 18.104.22.168. Check Read-During-Write Behavior 22.214.171.124. Controlling RAM Inference and Implementation 126.96.36.199. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 188.8.131.52. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 184.108.40.206. Simple Dual-Port, Dual-Clock Synchronous RAM 220.127.116.11. True Dual-Port Synchronous RAM 18.104.22.168. Mixed-Width Dual-Port RAM 22.214.171.124. RAM with Byte-Enable Signals 126.96.36.199. Specifying Initial Memory Contents at Power-Up
188.8.131.52. If Performance is Important, Optimize for Speed 184.108.40.206. Use Separate CRC Blocks Instead of Cascaded Stages 220.127.116.11. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 18.104.22.168. Take Advantage of Latency if Available 22.214.171.124. Save Power by Disabling CRC Blocks When Not in Use 126.96.36.199. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
188.8.131.52. Avoid Combinational Loops
Combinational loops are among the most common causes of instability and unreliability in digital designs. Combinational loops generally violate synchronous design principles by establishing a direct feedback loop that contains no registers.
Avoid combinational loops whenever possible. In a synchronous design, feedback loops should include registers. For example, a combinational loop occurs when the left-hand side of an arithmetic expression also appears on the right-hand side in HDL code. A combinational loop also occurs when you feed back the output of a register to an asynchronous pin of the same register through combinational logic.
Figure 1. Combinational Loop Through Asynchronous Control Pin
Combinational loops are inherently high-risk design structures for the following reasons:
- Combinational loop behavior generally depends on relative propagation delays through the logic involved in the loop. As discussed, propagation delays can change, which means the behavior of the loop is unpredictable.
- In many design tools, combinational loops can cause endless computation loops . Most tools break open combinational loops to process the design. The various tools used in the design flow may open a given loop differently, and process it in a way inconsistent with the original design intent.
Did you find the information on this page useful?