Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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2.7. Designing with Low-Level Primitives

Low-level HDL design is the practice of using low-level primitives and assignments to dictate a particular hardware implementation for a piece of logic. Low-level primitives are small architectural building blocks that assist you in creating your design.

With the Intel® Quartus® Prime software, you can use low-level HDL design techniques to force a specific hardware implementation that can help you achieve better resource utilization or faster timing results.

Note: Using low-level primitives is an optional advanced technique to help with specific design challenges. For many designs, synthesizing generic HDL source code and Intel FPGA IP cores give you the best results.

Low-level primitives allow you to use the following types of coding techniques:

  • Instantiate the logic cell or LCELL primitive to prevent Intel® Quartus® Prime Standard Edition integrated synthesis from performing optimizations across a logic cell
  • Create carry and cascade chains using CARRY, CARRY_SUM, and CASCADE primitives
  • Instantiate registers with specific control signals using DFF primitives
  • Specify the creation of LUT functions by identifying the LUT boundaries
  • Use I/O buffers to specify I/O standards, current strengths, and other I/O assignments
  • Use I/O buffers to specify differential pin names in your HDL code, instead of using the automatically-generated negative pin name for each pair

For details about and examples of using these types of assignments, refer to the Designing with Low-Level Primitives User Guide.