2.6.6. Cyclic Redundancy Check Functions
CRC functions typically use wide XOR gates to compare the data. The way synthesis tools flatten and factor these XOR gates to implement the logic in FPGA LUTs can greatly impact the area and performance results for the design. XOR gates have a cancellation property that creates an exceptionally large number of reasonable factoring combinations, so synthesis tools cannot always choose the best result by default.
The 6-input ALUT has a significant advantage over 4‑input LUTs for these designs. When properly synthesized, CRC processing designs can run at high speeds in devices with 6-input ALUTs.
The following guidelines help you improve the quality of results for CRC designs in Intel FPGA devices.
If Performance is Important, Optimize for Speed
Use Separate CRC Blocks Instead of Cascaded Stages
Use Separate CRC Blocks Instead of Allowing Blocks to Merge
Take Advantage of Latency if Available
Save Power by Disabling CRC Blocks When Not in Use
Initialize the Device with the Synchronous Load (sload) Signal
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