Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
Document Table of Contents

1. Recommended Design Practices

Updated for:
Intel® Quartus® Prime Design Suite 18.1
This document is part of a collection. You can download the entire collection as a single PDF: Intel® Quartus® Prime Standard Edition User Guides - Combined PDF link
This chapter provides design recommendations for Intel® FPGA devices. This chapter also describes the Intel® Quartus® Prime Design Assistant. The Design Assistant checks your design for violations of Intel’s design recommendations

Current FPGA applications have reached the complexity and performance requirements of ASICs. In the development of complex system designs, design practices have an enormous impact on the timing performance, logic utilization, and system reliability of a device. Well-coded designs behave in a predictable and reliable manner even when retargeted to different families or speed grades. Good design practices also aid in successful design migration between FPGA and ASIC implementations for prototyping and production.

For optimal performance, reliability, and faster time-to-market when designing with Intel FPGA devices, you should adhere to the following guidelines:

  • Understand the impact of synchronous design practices
  • Follow recommended design techniques, including hierarchical design partitioning, and timing closure guidelines
  • Take advantage of the architectural features in the targeted device