2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
188.8.131.52. Use Synchronous Memory Blocks 184.108.40.206. Avoid Unsupported Reset and Control Conditions 220.127.116.11. Check Read-During-Write Behavior 18.104.22.168. Controlling RAM Inference and Implementation 22.214.171.124. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 126.96.36.199. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 188.8.131.52. Simple Dual-Port, Dual-Clock Synchronous RAM 184.108.40.206. True Dual-Port Synchronous RAM 220.127.116.11. Mixed-Width Dual-Port RAM 18.104.22.168. RAM with Byte-Enable Signals 22.214.171.124. Specifying Initial Memory Contents at Power-Up
126.96.36.199. If Performance is Important, Optimize for Speed 188.8.131.52. Use Separate CRC Blocks Instead of Cascaded Stages 184.108.40.206. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 220.127.116.11. Take Advantage of Latency if Available 18.104.22.168. Save Power by Disabling CRC Blocks When Not in Use 22.214.171.124. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
126.96.36.199. Use Synchronous Memory Blocks
Memory blocks in Intel FPGA are synchronous. Therefore, RAM designs must be synchronous to map directly into dedicated memory blocks. For these devices, Intel® Quartus® Prime synthesis implements asynchronous memory logic in regular logic cells.
Synchronous memory offers several advantages over asynchronous memory, including higher frequencies and thus higher memory bandwidth, increased reliability, and less standby power. To convert asynchronous memory, move registers from the datapath into the memory block.
A memory block is synchronous if it has one of the following read behaviors:
- Memory read occurs in a Verilog HDL always block with a clock signal or a VHDL clocked process. The recommended coding style for synchronous memories is to create your design with a registered read output.
- Memory read occurs outside a clocked block, but there is a synchronous read address (that is, the address used in the read statement is registered). Synthesis does not always infer this logic as a memory block, or may require external bypass logic, depending on the target device architecture. Avoid this coding style for synchronous memories.
Note: The synchronous memory structures in Intel FPGA devices can differ from the structures in other vendors’ devices. For best results, match your design to the target device architecture.
This chapter provides coding recommendations for various memory types. All the examples in this document are synchronous to ensure that they can be directly mapped into the dedicated memory architecture available in Intel FPGAs.
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