2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
220.127.116.11. Use Synchronous Memory Blocks 18.104.22.168. Avoid Unsupported Reset and Control Conditions 22.214.171.124. Check Read-During-Write Behavior 126.96.36.199. Controlling RAM Inference and Implementation 188.8.131.52. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 184.108.40.206. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 220.127.116.11. Simple Dual-Port, Dual-Clock Synchronous RAM 18.104.22.168. True Dual-Port Synchronous RAM 22.214.171.124. Mixed-Width Dual-Port RAM 126.96.36.199. RAM with Byte-Enable Signals 188.8.131.52. Specifying Initial Memory Contents at Power-Up
184.108.40.206. If Performance is Important, Optimize for Speed 220.127.116.11. Use Separate CRC Blocks Instead of Cascaded Stages 18.104.22.168. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 22.214.171.124. Take Advantage of Latency if Available 126.96.36.199. Save Power by Disabling CRC Blocks When Not in Use 188.8.131.52. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
2.6.1. Tri-State Signals
Use tri-state signals only when they are attached to top-level bidirectional or output pins.
Avoid lower-level bidirectional pins. Also avoid using the Z logic value unless it is driving an output or bidirectional pin. Even though some synthesis tools implement designs with internal tri-state signals correctly in Intel FPGA devices using multiplexer logic, do not use this coding style for Intel FPGA designs.
Note: In hierarchical block-based design flows, a hierarchical boundary cannot contain any bidirectional ports, unless the lower-level bidirectional port is connected directly through the hierarchy to a top-level output pin without connecting to any other design logic. If you use boundary tri-states in a lower-level block, synthesis software must push the tri-states through the hierarchy to the top level to make use of the tri-state drivers on output pins of Intel FPGA devices. Because pushing tri-states requires optimizing through hierarchies, lower-level tri-states are restricted with block-based design methodologies.
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