Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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2.4.3. Inferring Shift Registers in HDL Code

To infer shift registers, synthesis tools detect a group of shift registers of the same length, and convert them to an Intel FPGA shift register IP core.

For detection, all shift registers must have the following characteristics:

  • Use the same clock and clock enable
  • No other secondary signals
  • Equally spaced taps that are at least three registers apart

Synthesis recognizes shift registers only for device families with dedicated RAM blocks. Intel® Quartus® Prime Standard Edition integrated synthesis uses the following guidelines:

  • The Intel® Quartus® Prime software determines whether to infer the Intel FPGA shift register IP core based on the width of the registered bus (W), the length between each tap (L), or the number of taps (N).
  • If the Auto Shift Register Recognition option is set to Auto, Intel® Quartus® Prime Standard Edition integrated synthesis determines which shift registers are implemented in RAM blocks for logic by using:
    • The Optimization Technique setting
    • Logic and RAM utilization information about the design
    • Timing information from Timing-Driven Synthesis
  • If the registered bus width is one (W = 1), Intel® Quartus® Prime synthesis infers shift register IP if the number of taps times the length between each tap is greater than or equal to 64 (N x L > 64).
  • If the registered bus width is greater than one (W > 1), and the registered bus width times the number of taps times the length between each tap is greater than or equal to 32 (W × N × L > 32), the Intel® Quartus® Prime synthesis infers Intel FPGA shift register IP core.
  • If the length between each tap (L) is not a power of two, Intel® Quartus® Prime synthesis needs external logic (LEs or ALMs) to decode the read and write counters, because of different sizes of shift registers. This extra decode logic eliminates the performance and utilization advantages of implementing shift registers in memory.

The registers that Intel® Quartus® Prime synthesis maps to the Intel FPGA shift register IP core, and places in RAM are not available in a Verilog HDL or VHDL output file for simulation tools, because their node names do not exist after synthesis.

Note: The Compiler cannot implement a shift register that uses a shift enable signal into MLAB memory; instead, the Compiler uses dedicated RAM blocks. To control the type of memory structure that implements the shift register, use the ramstyle attribute.