188.8.131.52. Inferring Latches Correctly
If latches or combinational loops in the design do not appear in the User Specified and Inferred Latches section, then Intel® Quartus® Prime synthesis did not infer the latch as a safe latch, so the latch is not considered glitch-free.
All combinational loops listed in the Analysis & Synthesis Logic Cells Representing Combinational Loops table in the Compilation Report are at risk of timing hazards. These entries indicate possible problems with the design that require further investigation. However, correct designs can include combinational loops. For example, it is possible that the combinational loop cannot be sensitized. This occurs when there is an electrical path in the hardware, but either:
- The designer knows that the circuit never encounters data that causes that path to be activated, or
- The surrounding logic is set up in a mutually exclusive manner that prevents that path from ever being sensitized, independent of the data input.
For 4-input LUT-based devices, such as Stratix® devices, the Cyclone® series, and MAX® II devices, all latches in the User Specified and Inferred Latches table with a single LUT in the feedback loop are free of timing hazards when a single input changes. Because of the hardware behavior of the LUT, the output does not glitch when a single input toggles between two values that are supposed to produce the same output value, such as a D-type input toggling when the enable input is inactive or a set input toggling when a reset input with higher priority is active. This hardware behavior of the LUT means that no cover term is required for a loop around a single LUT. The Intel® Quartus® Prime software uses a single LUT in the feedback loop whenever possible. A latch that has data, enable, set, and reset inputs in addition to the output fed back to the input cannot be implemented in a single 4‑input LUT. If the Intel® Quartus® Prime software cannot implement the latch with a single-LUT loop because there are too many inputs, the User Specified and Inferred Latches table indicates that the latch is not free of timing hazards.
For 6-input LUT-based devices, Intel® Quartus® Prime synthesis implements all latch inputs with a single adaptive look-up table (ALUT) in the combinational loop. Therefore, all latches in the User-Specified and Inferred Latches table are free of timing hazards when a single input changes.
If Intel® Quartus® Prime synthesis report lists a latch as a safe latch, other optimizations, such as physical synthesis netlist optimizations in the Fitter, maintain the hazard-free performance. To ensure hazard-free behavior, only one control input can change at a time. Changing two inputs simultaneously, such as deasserting set and reset at the same time, or changing data and enable at the same time, can produce incorrect behavior in any latch.
Intel® Quartus® Prime synthesis infers latches from always blocks in Verilog HDL and process statements in VHDL. However, Intel® Quartus® Prime synthesis does not infer latches from continuous assignments in Verilog HDL, or concurrent signal assignments in VHDL. These rules are the same as for register inference. The Intel® Quartus® Prime synthesis infers registers or flipflops only from always blocks and process statements.
Verilog HDL Set-Reset Latch
module simple_latch ( input SetTerm, input ResetTerm, output reg LatchOut ); always @ (SetTerm or ResetTerm) begin if (SetTerm) LatchOut = 1'b1; else if (ResetTerm) LatchOut = 1'b0; end endmodule
VHDL Data Type Latch
LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY simple_latch IS PORT ( enable, data : IN STD_LOGIC; q : OUT STD_LOGIC ); END simple_latch; ARCHITECTURE rtl OF simple_latch IS BEGIN latch : PROCESS (enable, data) BEGIN IF (enable = '1') THEN q <= data; END IF; END PROCESS latch; END rtl;
Verilog Continuous Assignment Does Not Infer Latch
The following example shows a Verilog HDL continuous assignment that does not infer a latch in the Intel® Quartus® Prime software:
assign latch_out = (~en & latch_out) | (en & data);
The behavior of the assignment is similar to a latch, but it may not function correctly as a latch, and its timing is not analyzed as a latch. Intel® Quartus® Prime Standard Edition integrated synthesis also creates safe latches when possible for instantiations of an Altera latch IP core. Altera latch IPs allow you to define a latch with any combination of data, enable, set, and reset inputs. The same limitations apply for creating safe latches as for inferring latches from HDL code.
Inferring the Altera latch IP core in another synthesis tool ensures that Intel® Quartus® Prime synthesis also recognizes the implementation as a latch. If a third-party synthesis tool implements a latch using the Altera latch IP core, Intel® Quartus® Prime Standard Edition integrated synthesis reports the latch in the User-Specified and Inferred Latches table, in the same manner as it lists latches you define in HDL source code. The coding style necessary to produce an Altera latch IP core implementation depends on the synthesis tool. Some third-party synthesis tools list the number of Altera latch IP cores that are inferred.
The Fitter uses global routing for control signals, including signals that synthesis identifies as latch enables. In some cases, the global insertion delay decreases timing performance. If necessary, you can turn off the Intel® Quartus® Prime Global Signal logic option to manually prevent the use of global signals. The Global & Other Fast Signals table in the Compilation Report reports Global latch enables.
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